Inter-processor communication is frequently used in multi-processor systems. Multi-processor systems may reside on a single chip, such as, for example, an application-specific integrated circuit (ASIC). Alternatively, multi-processor systems may be made up by processors that reside on different chips in an electronic device or even by processors residing in separate devices, possibly geographically separated. The processors of a multi-processor system may be standard, off-the-shelf processors, or they may be special purpose processors specifically designed for certain tasks or conditions.
Each processor of a multi-processor system may have an operating system running on it. The cores of the operating systems need to communicate in a way that is transparent to the applications running on the respective operating systems. Inter-processor communication may for example involve a data message that needs to be transferred from a memory unit associated with a first one of the processors in the multi-processor system to a memory unit associated with a second one of the processors in the multi-processor system. The need for transferring the data message may, for example, be initiated by a thread associated with the second processor if the thread is using a service on the first processor
Generally speaking, the data message to be transferred comprises a payload portion, i.e. the data that needs to be communicated. The payload portion is of a particular size, which may be expressed, for example, in a number of bytes. The size of the payload portion may vary between different messages that need to be communicated. Since the size may vary and the processor that is to receive the data message has to support reception of messages of all possible sizes, may not be advantageous to have a pre-allocated fixed-size buffer in the memory unit associated with the receiving processor for storing of the received data message. This is because such a solution generally results in a large amount of so-called slack, that is, unused memory that is spread out over the memory unit.
Consequently, the receiving processor (or the receiving processor sub-system) needs to get information regarding the size of the message to be able to allocate a buffer of appropriate size prior to receiving the payload portion of the message. This information may be transmitted by the sending processor prior to transmitting the payload portion. The reception of the size information may generate an interrupt signal in the receiving processor. Then, in response to the interrupt signal, the receiving processor recognizes the size and allocates a buffer of appropriate size in the memory unit associated with the receiving processor. In some implementations, a second interrupt signal is generated in the receiving processor when the buffer has been allocated.
When the buffer has been allocated, the payload can be received and stored in the allocated buffer. For example, the payload can be received and stored in response to the second interrupt signal or as part of executing the procedure in response to the first interrupt signal. When the storing of the payload of the data message in the buffer is completed, yet another interrupt signal may be generated in the receiving processor. This interrupt signal has the purpose of informing the receiving processor central processing unit (CPU) that the data message has been received and stored. This entire procedure has to be repeated for each data message that needs to be communicated between processors of the multi-processor system.
A high frequency of interrupt signals in a processor of a multi-processor system constitutes a severe disadvantage in many situations. For each interrupt signal, a number of steps, such as enter, execute and exit operations, have to be executed by the operating system that runs on that particular processor even when the interrupt signal conveys a fairly simple interrupt request such as, for example, a key stroke or an external hardware request. When the interrupt signal conveys a more complicated interrupt request such as, for example, a nested interrupt there may be even more steps to execute by the operating system.
Thus, the frequency of interrupt signals may have large influence on the performance of processors in, for example, multi-processor systems. Lowering the frequency of interrupt signals may shorten the overall execution time of tasks performed by the operating system running on a processor. In particular when a multi-processor system resides on a single chip, it may be expected that the message transfer should be executed at very high speed, and hence lowering the number of interrupts needed for an inter-processor message transfer would be particularly desirable in such cases, although it would be advantageous in all multi-processor systems.
Another problem encountered in multi-processor systems is when data intended for a particular position in a memory unit may be written to another, unsuitable or erroneous, position in the memory unit or even in another memory unit. Such events may, for example, be the result of hacking, viruses or poorly written code. Furthermore, a hacking or virus attack may write its own data in a memory unit. In all such cases, a subsequent read access may result in completely different data than was intended.
A further disadvantage of some multi-processor systems is when a protocol, such as a shared memory protocol, is used in which memory pointers are exchanged between different processors. In such solutions, there is a risk that e.g. a virus or hacker may tap into the connection, read the pointer, and use the memory address indicated by the pointer to download data or to download and run code on the receiving processor. Alternatively, a virus or hacker may alter the pointer and thereby cause the intended data to be written in an erroneous memory location.
Thus, there is a need for communicating a data message between processors in a multi-processor system while generating as few interrupt signals as possible in the receiving processor and as little slack as possible in a memory unit associated with the receiving processor. Furthermore, there is a need to prevent illegal or unwanted memory use in a multi-processor system.